TDCs are used to measure the time interval between two events by a small quantization step that creates a time resolution. High resolution TDCs have become increasingly popular for time-of-flight measurement, jitter measurement, clock data recovery, measurement and instrumentation, and digital phase-locked loops. Time resolution, detectable range, measurement time, power consumption and die area are most important concerns in TDC designs. Similar to any other analog to digital converter, the quantization step is the major parameter of TDC that determines the system performance in all the applications stated above. Time resolution has previously been limited by the propagation delay of the inverter and therefore has become a critical criteria in the assessment of TDC design.
A prior art delay line based TDC 100 is illustrated in FIG. 1. The delay line based TDC 100 comprises a few delay stages 102 and D flip-flops (DFFs) 104. The DFFs are coupled in series down a first delay line 106, and the DFFs are coupled to the output of each delay stage 102 and to an input line 108. In operation a first event signal is propagated down the delay line 106 such that it is slowed down by each delay stage 102 before reaching an input of each DFF 104. Each delay stage 102 will cause the first event signal to repeat the logical “01” or “10” transition after imposing a certain amount of delay on the signal. The second event signal then triggers all the DFFs 104 to sample the outputs of all delay stages 102 causing the DFFs 104 to output a logical 1 until the second event signal passes the first event signal. These sampled values, which are output along an output line 110 are then summed up to a number N. As a result, the measured time interval between these two event signals is able to be calculated usingTin=N*tdelay where the tdelay is the delay of a single delay stage 102. The drawback of these delay line based TDCs 100 is their large quantization steps (time resolution), which cannot be reduced easily.
The Vernier delay line 200 shown in FIG. 2, although substantially similar to the delay line described above, is one popular technique for TDCs to improve the time resolution. In this case, the first event signal again propagates through a slow delay line 206 comprising a number of delay stages 202A, however this time the second event signal propagates through a fast delay line 208 also having a number of delay stages 202B. The fast delay line 208 has a propagation delay per stage of tf and the slow delay line 206 has a propagation delay per stage of tS. Each DFF 204 will output a logical 1 once the second event signal arrives earlier than the first event signal to the inputs of the DFF 204. Otherwise the DFF 204 outputs a logical 0. Thus, in this case the time interval between the first and second event signals is given byTin=N*Δt=N*(tf−tS)where Δt is much less than both tf and tS. Due to the improved time resolution, the Vernier delay line (VDL) TDC 200 needs a significantly larger amount of stages 202A, 202B, has a longer measurement time and requires larger power consumption in order to quantize the given time interval. Therefore, the prior art VDL TDC 200 has small detectable range and must occupy a large area, which limit its application.